Robustness Analysis of Controllable-Polarity Silicon Nanowire Devices and Circuits

Substantial downscaling of the feature size in current CMOS technology has confronted digital designers with serious challenges including short channel effect and high amount of leakage power. To address these problems, emerging nano-devices, e.g., Silicon NanoWire FET (SiNWFET), is being introduced by the research community. These devices keep on pursuing Mooreâs Law by improving channel electrostatic controllability, thereby reducing the Off âstate leakage current. In addition to these improvements, recent developments introduced devices with enhanced capabilities, such as Controllable-Polarity (CP) SiNWFETs, which make them very interesting for compact logic cell and arithmetic circuits. At advanced technology nodes, the amount of physical controls, during the fabrication process of nanometer devices, cannot be precisely determined because of technology fluctuations. Consequently, the structural parameters of fabricated circuits can be significantly different from their nominal values. Moreover, giving an a-priori conclusion on the variability of advanced technologies for emerging nanoscale devices, is a difficult task and novel estimation methodologies are required. This is a necessity to guarantee the performance and the reliability of future integrated circuits. Statistical analysis of process variation requires a great amount of numerical data for nanoscale devices. This introduces a serious challenge for variability analysis of emerging technologies due to the lack of fast simulation models. One the one hand, the development of accurate compact models entails numerous tests and costly measurements on fabricated devices. On the other hand, Technology Computer Aided Design (TCAD) simulations, that can provide precise information about devices behavior, are too slow to timely generate large enough data set. In this research, a fast methodology for generating data set for variability analysis is introduced. This methodology combines the TCAD simulations with a learning algorithm to alleviate the time complexity of data set generation. Another formidable challenge for variability analysis of the large circuits is growing number of process variation sources. Utilizing parameterized models is becoming a necessity for chip design and verification. However, the high dimensionality of parameter space imposes a serious problem. Unfortunately, the available dimensionality reduction techniques cannot be employed for three main reasons of lack of accuracy, distribution dependency of the data points, and finally incompatibility with device and circuit simulators. We propose a novel technique of parameter selection for modeling process and performance variation. The proposed technique efficiently addresses the aforementioned problems. Appropriate testing, to capture manufacturing defects, plays an important role on the quality of integrated circuits. Compared to conventional CMOS, emerging nano-devices such as CP-SiNWFETs have different fabrication process steps. In this case, current fault models must be extended for defect detection. In this research, we extracted the possible fabrication defects, and then proposed a fault model for this technology. We also provided a couple of test methods for detecting the manufacturing defects in various types of CP-SiNWFET logic gates. Finally, we used the obtained fault model to build fault tolerant arithmetic circuits with a bunch of superior properties compared to their competitors

A Fast TCAD-based Methodology for Variation Analysis of Emerging Nano-Devices

Variability analysis of nanoscale transistors and circuits is emerging as a necessity at advanced technology nodes. Technology Computer Aided Design (TCAD) tools are powerful ways to get an accurate insight of Process Variations (PV). However, obtaining both fast and accurate device simulations is impractical with current TCAD solvers. In this paper, we propose an automated output prediction method suited for fast PV analysis. Coupled with TCAD simulations, our methodology can substantially reduce the time complexity and cost of variation analysis for emerging technologies. We overcome the simulation obstacles and preserve accuracy, using a neural network based regression to predict the output of individual process simula- tions. Experiments indicate that, after the training process, the proposed methodology effectively accelerate TCAD-based PV simulations close to compact-model-based simulations. Therefore, the methodology can be an excellent opportunity in enabling extensive statistical simulations such as Monte-Carlo for emerging nano-devices

Efficient Statistical Parameter Selection for Nonlinear Modeling of Process/Performance Variation

With the growing number of process variation sources in deeply nano-scaled technologies, parameterized device and circuit modeling is becoming very important for chip design and verification. However, the high dimensionality of parameter space, for process variation analysis, is a serious modeling challenge for emerging VLSI technologies. These parameters correspond to various inter-die and intra-die variations, and considerably increase the difficulties of design validation. Today’s response surface models and most commonly used parameter reduction methods, such as Principal Component Analysis (PCA) and Independent Component Analysis (ICA), limit parameter reduction to linear or quadratic form and they do not address the higher order of nonlinearity among process and performance parameters. In this paper, we propose and validate a feature selection method to reduce the circuit modeling complexity associated with high parameter dimensionality. This method relies on a learning-based nonlinear sparse regression, and performs a parameter selection in the input space rather than creating a new space. This method is capable of dealing with mixed Gaussian and non-Gaussian parameters and results in a more precise parameter selection considering statistical nonlinear dependencies among input and output parameters. The application of this method is demonstrated in digital circuit timing analysis in both FinFET and Silicon Nanowire technologies. The results confirm the efficiency of this method to significantly reduce the number of required simulations while keeping estimation error small

A Fault Tolerant Ripple-Carry Adder with Controllable-Polarity Transistors

This paper deals with the effects of faults on circuits implemented with controllable-polarity transistors. We propose a new fault model that suits the characteristics of these devices, and report the results of a SPICE-based analysis of the effects of faults on the behavior of some basic gates implemented with them. Hence, we show that the considered devices are able to intrinsically tolerate a rather high number of faults. We finally exploit this property to build a robust and scalable adder which is shown to tolerate all single faults and more than 99.5% of the double faults. Its area, performance and leakage power characteristics are improved by 15%, 18% and 12%, respectively, when compared to an equivalent FinFET solution at 22-nm technology node